1. Technical Field
The present invention relates to semiconductor devices and portable electronic device. More specifically, the invention relates to a semiconductor device using a dynamic threshold transistor and a substrate bias-variable transistor, as well as a portable electronic device using this semiconductor device.
2. Background Art
In order to decrease power consumption in CMOS (Complementary Metal Oxide Semiconductor) circuits using MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), it is most effective to lower the power supply voltage. However, merely lowering the power supply voltage would cause the drive current of MOSFETs to lower, resulting in a lower operating speed of the circuit. This phenomenon is known to become noticeable as the power supply voltage becomes a triple or less of the threshold of the transistor. Although this phenomenon can be prevented by lowering the threshold, doing so would give rise to a problem of increases in off-leak current of MOSFETs. Therefore, the lower limit of the threshold is defined within a range over which the above problem does not occur. This in turn defines the limits of power consumption reduction since the lower limit of the threshold corresponds to the lower limit of the power supply voltage.
Conventionally, there has been proposed a dynamic-threshold transistor (hereinafter, referred to as DTMOS) which performs dynamic-threshold operations and which employs a bulk substrate for alleviation of the above-mentioned problem (Japanese Patent Laid-Open Publications HEI 10-22462, Novel Bulk Dynamic Threshold Voltage MOSFET (B-DTMOS) with Advanced Isolation (SITOS) and Gate to Shallow-Well Contact (SSS-C) Processes for Ultra Low Power Dual Gate CMOS, H. Kotaki et al., IEDM Tech. Dig., p. 459, 1996). The aforementioned DTMOS has a characteristic of a capability of obtaining high drive current with low power supply voltage by virtue of its effective threshold lowering in an ON state. The reason why the effective threshold of a DTMOS lowers in the ON state is that the gate electrode and the well region are electrically short-circuited.
The principle of operation of the N-type DTMOS is explained below. It is noted that the P-type DTMOS operates similarly with the polarity reversed. In the N-type DTMOS, when the gate electrode voltage is at a low level (in an OFF state), the P-type well region voltage is also at a low level, the effective threshold has no differences from normal MOSFETs. Therefore, the off current value (off-leak) is the same as in the case of normal MOSFETs.
On the other hand, when the gate electrode voltage is at a high level (in an ON state), the P-type well region voltage is also at a high level, and the effective threshold lowers by the substrate bias effect, so that the drive current increases compared with those of normal MOSFETs. Therefore, large drive current can be obtained with low power supply voltage while low leak current is maintained.
In a DTMOS, the gate electrode and the well region are electrically short-circuited. Therefore, as the gate electrode voltage changes, the well voltage also changes similarly. This accordingly requires the well region of each DTMOS to be mutually electrically isolated from the well regions of its neighboring MOSFETs. For this reason, the well region is made up of a shallow well region and a deep well region which are different in conductive type from each other. Furthermore, the shallow well regions of the respective DTMOSs are electrically isolated from one another by a device isolation region.
As a conventional method for suppressing off-leaks in low voltage drive and still obtaining high drive current, there has been a method in which the well-bias voltage is changed between standby and active states (Japanese Patent Laid-Open Publications HEI 6-216346 and 10-340998).
Hereinafter, a MOSFET in which the well bias is changed between standby and active states will be referred to as substrate bias-variable transistor.
The principle of operation of the N-type substrate bias-variable transistor is explained below. It is noted that the P-type substrate bias-variable transistor operates similarly with the polarity reversed. In an N-type substrate bias-variable transistor, when the circuit is in an active state, a 0 V or positive voltage (with a source voltage referenced) is applied from a bias generation circuit to the P-type well region. With a positive voltage applied to the P-type well region, the effective threshold lowers due to a substrate bias effect, and the drive current increases as compared with the case of normal MOSFETs. When the circuit is in a standby state, on the other hand, a negative voltage is applied from the bias generation circuit to the P-type well region. As a result of this, the effective threshold increases due to the substrate bias effect, and the off-leak decreases as compared with normal MOSFETs or DTMOSs.
Generally, in a circuit using substrate bias-variable transistors, whether the active state or the standby state is effectuated is selected from circuit block to circuit block. This is because providing the bias generation circuit for each device causes the number of devices and the circuit area to increase considerably. From these reasons, the P-type well region of an N-type MOSFET is common within a circuit block (the case is the same with the N-type well region of a P-type MOSFET). Accordingly, in a circuit block which is in an active state, a 0 V or positive voltage is applied to the well regions of all the N-type MOSFETs, so that the off-leak increases as compared with normal MOSFETs or DTMOSs (the case is the same also with the P-type MOSFETs).
In the circuit using substrate bias-variable transistors, MOSFETs within a circuit block have to share a well region. For this purpose, the depth of the bottom face of the device isolation region is set deeper than the depth of the junction between the source regions and drain regions of the MOSFETs and their shallow well region and, at the same time, shallower than the depth of the lower end of the shallow well region.
There has been disclosed a technique in which the DTMOS and the substrate bias-variable transistor are combined together to make the best of their respective advantages (Japanese Patent Laid-Open Publication HEI 10-340998).
FIG. 10 shows a cross-sectional view of a device fabricated by this technique. Referring to FIG. 10, there are shown, with reference numerals having the following denotations, a P-type semiconductor substrate 11, an N-type deep well region 12, a P-type deep well region 13, an N-type shallow well region 14, a P-type shallow well region 15, a device isolation region 16, an N-type MOSFET source region 17, an N-type MOSFET drain region 18, a P-type MOSFET source region 19, a P-type MOSFET drain region 20, an N+ diffusion layer 21 for providing contact with an N-type shallow well region, a P+ diffusion layer 22 for providing contact with a P-type shallow well region, a gate insulator 23, a gate electrode 24, a P-type substrate bias-variable transistor 25, an N-type substrate bias-variable transistor 26, an N-type DTMOS 27, a P-type DTMOS 28, a well-bias input terminal 29 for the P-type substrate bias-variable transistor, a well-bias input terminal 30 for the N-type substrate bias-variable transistor, and a fixed bias input terminal 31 for the P-type deep well region. In addition, although not shown, the gate electrode 24 and the P-type shallow well region 15 are electrically short-circuited in the N-type DTMOS 27, and the gate electrode 24 and the N-type shallow well region 14 are electrically short-circuited in the P-type DTMOS 28.
In the DTMOSs 27 and 28, the voltages of the shallow well regions 14 and 15 change according to the voltage of the gate electrode 24. In order to prevent changes of the voltages of the shallow well regions 14 and 15 from affecting shallow well regions of other devices, deep well regions 13 and 12 opposite in conductive type to the shallow well regions 14 and 15 are formed under those shallow well regions 14 and 15. Moreover, a device isolation region 16 is formed at enough depth to electrically isolate shallow well regions 14 and 15 of mutually neighboring devices. By doing so, the shallow well regions 14 and 15 are electrically isolated from shallow well regions 14 and 15 of neighboring devices. Meanwhile, shallow well regions 14, 15 of the substrate bias-variable transistors 25, 26 contained in one circuit block have to be provided in common. Therefore, under the P-type shallow well regions 15 of the N-type substrate bias-variable transistors 26 in FIG. 10, is formed the P-type deep well region 13, which is integrated with a P-type shallow well region 15 to form a common well region. To this P-type common well region, a voltage that differs between active and standby states is given via the well-bias input 30 for the N-type substrate bias-variable transistor 26. In order to prevent any effects on devices of other circuit blocks or DTMOS portion, the N-type deep well region 12 is formed further deeper in the substrate, by which the P-type deep well region 13 is electrically isolated.
Under the N-type shallow well region 14 of the P-type substrate bias-variable transistor 25 in FIG. 10, is formed the N-type deep well region 12, which is integrated with the N-type shallow well region 14 to form a common well region. To this N-type common well region, a voltage that differs between active and standby states is given via the well-bias input terminal 29 for the P-type substrate bias-variable transistor 25.
FIGS. 11 and 12 show the procedure of forming the deep well regions of this prior-art semiconductor device. As shown in FIG. 11, with photoresist 33 used as a mask, dopant injection for forming the P-type deep well region 13 is performed, and then dopant injection for forming an N-type deep well region 12a further deeper is performed. Next, as shown in FIG. 12, with photoresist 34 used as a mask, dopant injection for forming an N-type deep well region 12b is performed. In this case, the depth of the N-type deep well region 12b is set to a level similar to the depth of the P-type deep well region 13. By these steps, the N-type deep well regions 12a and 12b are integrated together, by which the P-type deep well region 13 is electrically isolated.
In this way, the substrate bias-variable transistors 25, 26 and the DTMOSs 27, 28 are formed on the same substrate 11, making it possible to realize a circuit making the best of their respective advantages.
In the conventional semiconductor device, shown in FIG. 10, in which the DTMOSs 27, 28 and the substrate bias-variable transistors 25, 26 are combined together, although the P-type deep well regions 13 can be electrically isolated, the N-type deep well region 12 is common within one substrate 11. Therefore, although the circuit block of the N-type substrate bias-variable transistors 26, 26 can be formed plurally within the same substrate 11, the circuit block of the P-type substrate bias-variable transistor 25, 25 cannot be formed plurally, so that a plurality of circuit blocks cannot be divided properly into circuit blocks of the active state and circuit blocks of the standby state. For example, even when only part of the P-type gsubstrate bias-variable transistors 25, 25 need to be put into active state, the entirety of the P-type substrate bias-variable transistors 25, 25 would come into an active state, causing the leak current to increase. As a result, the power consumption would increase.